In the design of an integrated circuit, it may be useful to provide a first array of memory having one set of operating constraints (such as registers) along with a second memory array (such as a static RAM or a dynamic RAM) having a second set of operating constraints, with both memory arrays sharing a single data bus. A simplified block diagram of this circuitry is shown in FIG. 1. The register array 10 is coupled to a global data bus 12 via a register address decoder 14 including column decoder 14a, row decoder 14b and control circuitry 14c. Similarly, a RAM array 16 is coupled to the global bus 12 via RAM address decoder 18, including column decoder 18a, row decoder 18b and control circuitry 18c. Central read/write sense amp circuitry 20 is coupled to the global bus 12. The sense amp provides the data output responsive to reading the data on the global bus 12.
Data is developed on the register array 10 responsive to signals from the register address decode circuitry 14. Similarly, data is developed on the bitlines of the RAM array 16 responsive to signals from the RAM address decode circuitry 18. The address signal is input to both the register address decode circuitry 14 and the RAM address decode circuitry 18. Because it is difficult to identically decode the address signals to both the register array 10 and RAM array 16, a false signal may be generated on the data bus by one array which must be overcome by the other array, causing access push-out, where the access time is increased due to the longer time period until the bus data is valid. This problem is compounded where the devices used in one array (in this case, register array 10) generate a stronger signal than the devices used in the other array (in this case, RAM array 16) or where the bitline capacitance of one array (in this case, register array 10) is significantly less than the bitline capacitance in the other array (in this case, RAM array 16). In this case the push-out is increased.
The aforementioned problem is best understood in connection with the timing diagram of FIG. 2. At the time designated by point 30, the signal on the address lines is changing from an address corresponding to the memory space of the register array 10 to an address corresponding to the address space of the RAM array 16. After the address has changed, the ETD signal (Edge Transition Detection) generates a logical low pulse of predetermined duration starting at point 32. One effect of the logic low pulse of the ETD signal is a precharging of the global bus (DATA) at point 34. The row and column select lines of the register array 10, however, are not deselected responsive to the change in address until point 36. Hence, the precharged signal on the data lines will be affected by the signal on the column lines of the register array (which has not yet been deselected) resulting in the formation of a false signal at point 38. By the time the row and column select signals for the RAM are selected at point 40, a significant false signal has been generated on the data lines which must be overcome by the weaker devices (and higher column capacitance) of the RAM array 16. A true signal is not developed on the data lines until point 42.
Because of the independent addressing paths to the register array 10 and the RAM array 16, processing variations, temperature, voltages and the nature of the respective decode circuits, may result in time imbalances between the select-to-deselect time of the register address decode circuitry 22 and the deselect-to-select time of the RAM address decode circuitry 24. Consequently, the register array may drive the bus 12 for 1-2 nanoseconds after precharging which will result in a 5-6 nanosecond push-out on the data lines as the RAM array overcomes the false signal. As a result, the access time is significantly increased.
Therefore, a need has arisen in the industry for access control circuitry which overcomes the false signals otherwise generated by multiple memory arrays driving a single bus.